1. Field of the Invention
The present invention pertains to liquid crystal on silicon (LCOS) displays, and more particularly to improved pixel cell design for liquid crystal on silicon displays with enhanced voltage control.
2. Description of the Prior Art
To enhance the luminance and fill factor of liquid crystal projection displays, reflective LCD pixels are often used. These systems, referred to as Liquid Crystal on Silicon micro-displays (LCOS), utilize a large array of image pixels to achieve a high-resolution output of the input image. Each pixel of the display includes a liquid crystal layer sandwiched between a transparent electrode and a reflective pixel electrode. Typically, the transparent electrode is common to the entire display while the reflective pixel electrode is operative to an individual image pixel. A storage element, or other memory cell, is mounted beneath the pixels and can selectively direct a voltage on the pixel electrode. By controlling the voltage difference between the common transparent electrode and each of the reflective pixel electrodes, the optical characteristics of the liquid crystal can be controlled according to the image data being supplied. The storage element can be either an analog or a digital storage element although digital storage elements have become more common because of their resistance to charge decay in environments with high thermal or light loads
Liquid crystal on silicon (LCOS) microdisplay technology is still challenged by a need to reduce the cost of projection systems for consumer markets in the United States and abroad. One proposed method that has achieved limited success is to implement a system wherein a single LCOS microdisplay is able to modulate the needed three primary colors without exhibiting unacceptable flicker or image breakup. Previous LCOS projection systems have exhibited outstanding performance but have required complex optics and three separate microdisplays, one for each color. Successful single panel architectures to date have involved small, low resolution microdisplays operating in field sequential color mode because of the need to write two full sets of color fields (RGB) in the time previously allocated for one RGB frame to mitigate artifacts. Alternatively single panel frames have required the use of color filter material applied directly to the pixels of the display before assembly. This has also limited resolution because three times as many sub-pixels are required—one for each color.
Both approaches have limitations that must be overcome. Lower resolution is objectionable to some consumers. The continuing consumer trend to expect higher resolution has resulted in displays now being fielded in a new class of mobile telephones with a resolution of 900 by 600 (540,000 pixels) over a previous resolution of 480 pixels by 320 pixels (153,600 pixels)—a more than three fold increase in resolution in a display with an image diagonal of 3.5 inches. The color filter approach is more difficult to implement because of the inherent difficulties involved in applying filter material to pixels with dimensions on the order of 15 micrometers. For comparison the dimension of pixels in direct view displays are typically 100 micrometers. Improvements to resolution and function are clearly needed.
There are additional considerations beyond the problems cited above. As previously noted, operating in field sequential color mode requires substantial increases in the data rate to mitigate artifacts. The common artifacts include flicker, color breakup, and color cross coupling. Lesser artifacts that must be considered include dynamic false contours, lateral field artifacts, and motion blurring.
The perception of flicker is a fundamental aspect of human vision. Experimentation with flashing lights in the late 19th and early 20th centuries revealed that humans perceive flicker when a light is flashed at a rate between ½ Hertz and 60 Hertz. There is some variance among individuals as is often the case when dealing with different aspects of human vision. The upper limit of 60 Hz is at best approximate. The preceding description is often referred to as the Ferry-Porter Law.
This effect is important in the field of displays and especially in the field of color sequential displays. Inspection of the photopic curve (not presented here) plotting the sensitivity of the eye to color reveals a peak at about 550 nanometer wavelength; i.e., in the green spectrum. Thus displaying three colors (red, green, blue) in sequence 180 Hz creates a green flash rate of 60 Hz that is perceived as flicker. If a field sequential color display is operated at the same rate then observers will likely complain about flicker. Raising the rate to 75 Hz may reduce this somewhat but there are factors that may raise the minimum rate required to eliminate flicker. These include the overall brightness of the image, the depth of modulation, and the apparent size of the image (on the retina.) The upper limit of the flicker frequency rises as the brightness of the display rises. Depth of modulation is related in that raising the level of red and blue may reduce the perception of flicker. The effects of image size are less predictable but still a consideration. Practical field sequential color displays to date have been operated at a level of at least 360 color frames per second.
Color breakup occurs in part because much underlying data available for display is collected at 60 Hz and in part because the eye will follow moving objects moving faster than that as a part of its normal action. When a moving object is replicated in a field sequential color display the observer will tend to see color spreading because vision will move the eye to a predicted position for the object but the colors will be generated at the old position. This can be solved by motion interpolation but at some substantial cost. A better solution for a low cost display is to raise the frame rate for the green data. This changes the perception of the speed of the object and reduces the objectionable artifacts somewhat. Again, the solution requires increased data rates that translate into increased bandwidth.
A third artifact is color cross coupling. This occurs in a nematic liquid crystal display because the liquid crystal has a response time limit that may cause it to retain a slight memory of the state it was in for a previous color when the next LED generates its color. The observed effects of this problem are difficult to predict but in general objects created this way are often perceived as being less crisp than other images. To solve this problem several actions are possible. First the LEDs can all be gated off momentarily to allow the liquid crystal to settle to its new state. This, of course, causes a loss of brightness but it helps alleviate the problem. Second, the display can be driven to a dark state at the end of any given color field and may then be reloaded with data for the new color. This often takes place in conjunction with the gating of the LEDs. This requires that the drive to dark state take place as quickly as possible; an action that is limited by the time it takes to write the image array to the darks state as well as by the characteristics of the liquid crystal mode selected.
Solutions to the remaining artifacts are well known in the art. Each requires a level of data rate performance to implement solutions. Dynamic false contours are limited in nematic liquid crystal displays but may still somewhat visible if large temporal differences exist between adjacent gray levels. Reduction of temporal differences throughout the gray scale curve is the best way to reduce this. This same technique will reduce some of the lateral field effects in liquid crystal but ultimately the anchoring energy of the liquid crystal alignment and the pretilt of the cell. Motion blurring in particular may require motion interpolation as previously noted but an enhanced liquid crystal response time may assist with this as well. All of these require a substantial investment of time and resources that are normal for the development of products.
A brief review of the functioning of liquid crystal in a display is appropriate to support the disclosure of the invention. In a nematic liquid crystal display the liquid crystal layer rotates the polarization of light that passes through it, the extent of the polarization rotation depending on the root-mean-square (RMS) voltage that is applied across the liquid crystal layer. (The incident light on a reflective liquid crystal display thus is of one polarization and the reflected light associated with “on state” is normally of the orthogonal polarization.) The reason that the degree of polarization change depends on the RMS voltage is well known to those skilled in the art—it is the foundation of all liquid crystal displays.
Therefore, by applying varying voltages to the liquid crystal, the ability of the liquid crystal device to transmit light can be controlled. Since in a digital control application, the pixel drive voltage is either turned to dark state (off) or to bright state (on), certain modulation schemes must be incorporated into the voltage control in order to achieve a desired gray scale that is between the totally on and totally off positions. It is well known that the liquid crystal will respond to the RMS voltage of the drive waveform in those instances where the liquid crystal response time is slower than the modulation waveform time. The use of pulse-width modulation (PWM) is a common way to drive these types of digital circuits. In one type of PWM, varying gray scale levels are represented by multi-bit words (i.e. a binary number) that are converted into a series of pulses. The time averaged RMS voltage corresponds to a specific voltage necessary to maintain a desired gray scale.
Various methods of pulse width modulation are known in the art. One such example is binary-weighted pulse-width-modulation, where the pulses are grouped to correspond to the bits of a binary gray scale value. The resolution of the gray scale can be improved by adding additional bits to the binary gray scale value. For example, if a four-bit word is used, the time in which a gray scale value is written to each pixel, often referred to as frame time, is divided into fifteen intervals, often referred to as subframes, resulting in sixteen possible gray scale values (24 possible values). An 8-bit binary gray scale value would result in 255 intervals and 256 possible gray scale values (28 possible values).
Since most nematic liquid crystal materials only respond to the magnitude of an applied voltage, and not to the polarity of a voltage, a positive or negative voltage, of the same magnitude, applied across the liquid crystal material will normally result in the same optical properties (polarization) of the liquid crystal. However, the inherent physical characteristics of liquid crystal materials cause deterioration in the performance of the liquid crystal material due to an ionic migration or “drift” when a DC voltage is applied to them. A DC current will cause the contaminants always present in liquid crystal materials to drift toward one alignment surface or the other, if the same voltage polarity is continuously applied. This will result in the contaminants plating out onto the alignment layer with the result in that the liquid crystal material will begin to “stick” at an orientation and not respond fully to the drive voltages. This effect is manifested by the appearance of a ghost image of the previous image that is objectionable to viewers. Even highly purified liquid crystal materials have a certain level of ionic impurities within their composition (e.g. a negatively charged sodium ion). In order to maintain the accuracy and operability of the liquid crystal display, this phenomenon must be controlled. In order to prevent this type of “drift”, the RMS voltage applied to the liquid crystal must be modified so that alternating voltage polarities are applied to the liquid crystal. In this situation, the frame time of the PWM is divided in half During the first half of the frame the modulation data is applied on the pixel electrode according to the predetermined voltage control scheme. During the second half of the frame time, the complement of the modulation data is applied to the pixel electrode. When the common transparent electrode is maintained at its initial voltage state, typically high, this results in a net DC voltage component of zero volts. This technique generally referred to as “DC Balancing” technique is applied to avoid the deterioration of the liquid crystal without changing the RMS voltage being applied across the liquid crystal pixel and without changing the image that is displayed through the LCD panel. The requirement for DC balance is well known in the art.
Modulation schemes that are employed to drive the liquid crystal pixel elements must therefore be able to accurately control the amount of time the pixel “on” and “off”, in order to achieve a desired gray scale from the pixel. The degree of rotation of light that occurs follows the RMS voltage across the liquid crystal pixel. The degree of rotation in turn affects directly the intensity of the light that is visible to the observer. In this manner modulating voltages influences the intensity perceived by an observer. In this manner gray scale differences are created. The combination of all of the pixels in a display array results in an image being displayed through the LC device. In addition to controlling the root-mean square (RMS) voltage that applied to the pixel, the polarity of the voltage must be continuously reversed so that deterioration of the liquid crystal is avoided.
The electro-optical properties of many liquid crystal devices cause them to produce a maximum brightness at a certain RMS voltage (VSAT), and a minimum brightness at another RMS voltage (VTT). The relationship between the two voltages changes depending on whether the electro-optic mode is normally-black (NB) or normally-white (NW) with “normal” meaning un-driven or only lightly driven. Applying an RMS voltage of VSAT results in a bright cell, or full light reflection, while applying an RMS voltage of VTT results in a dark cell, or minimal light output. In the case of a normally white material decreasing the RMS voltage to a value below that of VSAT, may reduce the brightness of the cell rather than maintaining it at the full light reflection level. Likewise increasing the RMS voltage to a value above that of VTT, may normally increase the brightness of the cell somewhat rather than maintaining it at the zero light reflection level. At RMS voltages between VSAT and VTT in a NW mode the brightness decreases as the RMS voltage increases. The voltage range between VTT and VSAT therefore defines the useful range of the electro-optical curve for a particular liquid crystal material. It follows that RMS voltages outside of this range are not useful and will cause gray scale distortions if applied to the crystal pixels. It is therefore desirable to confine the RMS voltages applied to the pixels to this useful range between VSAT and VTT. Many known display systems drive the logic circuitry with voltages that are outside of the useful range of the liquid crystal, and applying these voltages directly onto the pixel electrode results in. wasted power. For example, logic circuitry may operate at 0 and 5 volts or 0 and 3.3 volts. If the useful range of the liquid crystal material is inside of this range, more time and power must be expended to achieve RMS voltages that are within the useful range. In a system that has a useful VTT to VSAT range of 1.0 to 2.5 volts and that has logic circuitry that operates at 0 to 5 volts, in order to achieve an RMS voltage of 2.5 volts, the pixel must see an equal amount of the 0 volt state and the 5 volt state over a time frame in order to achieve an RMS voltage of 2.5 volts. It is much more efficient for the liquid crystal drive logic circuitry to operate at the VSAT and VTT levels, rather than at levels outside of the VSAT to VTT range. This would make the time averaging simpler and faster and less power would be required to drive the same systems. For these reasons, it is desirable to confine the RMS voltages to the useful range of the electro-optical response curve of the liquid crystal material.
Another example of display system is disclosed in U.S. Pat. No. 6,005,558. A display system includes a memory element coupled to a multiplexer. Depending on the state of the memory element, the multiplexer directs one of two predetermined voltages onto a pixel electrode. The multiplexer is situated externally to the memory cell and is controlled by external circuitry to operate in conjunction with DC balance and data load operations. In the disclosed invention, operation of the multiplexer external to the cell requires that the voltages delivered via the rails to the cell be modulated to provide DC balance. This adds substantially to the complexity of the device because the modulated voltage must be correct in all respects as these same voltages are used to drive the pixel mirrors and thus achieve DC balance. Design of a line that can propagate a number of different voltages across long lines that must accurate in all cases is a significant design constraint. Furthermore, the disclosed invention requires that all elements be globally addressed to function. All these technical difficulties limit the effectiveness of the above inventions in providing practical solutions to the above-mentioned limitations.
patent application Ser. No. 10/329,645, now U.S. Pat. No. 7,468,717, filed by an inventor of this Application, discloses a pixel display configuration by providing a voltage controller in each pixel control circuit for controlling the voltage inputted to the pixel electrodes. The controller includes a function of multiplexing the voltage input to the pixel electrodes and also a bit buffering and decoupling function to decouple and flexibly change the input voltage level to the pixel electrodes. The rate of DC balancing can be increased to one KHz and higher to mitigate the possibility of DC offset effects and the image sticking problems caused by slow DC balancing rates. U.S. Pat. No. 7,468,717 further discloses an enabling technology for switching from one DC balance state to another without rewriting the data onto the panels. Therefore, the difficulties of applying a high voltage CMOS designs are resolved. Standard CMOS technologies can be applied to manufacture the storage and control panel for the LCOS displays with lower production cost and higher yields. The DC-balancing controller of U.S. Pat. No. 7,468,717 is implemented with a ten-transistor (10-T) configuration comprising two p-channel MOSFET transistors. While the controller is efficiently implemented, it does have a technical limitation due to a constraint that the p-channel MOSFET transistors are not effective in pulling down the voltage of the pixel mirror. The lower voltage limit V0 that the controller can assert on the pixel must set to 1.0 to 1.3 volts above the semiconductor ground voltage VSS with the precise voltage depending on the design details of the circuits. The limitation occurs due to the fact that a p-channel MOSFET transistor is strong in pulling the voltage up to VDD while weak in pulling down the voltage to VSS.
application Ser. No. 10/413,649, now U.S. Pat. No. 7,443,374, filed by an inventor of this application, discloses an improvement on the previously mentioned invention that eliminates the voltage restriction on the drive voltage by replacing the DC balance circuit with a new circuit that is able to operate in a voltage environment with V0 as low as VSS or perhaps even lower. Implementing the improved DC balance does solve the problem but requires two additional transistors and also requires that break-before-make circuits be added to the peripheral circuitry.
application Ser. No. 10/742,262, now U.S. Pat. No. 7,088,329, filed by an inventor of this application, discloses a different operating mode for the circuits disclosed in Ser. No. 10/413,649, wherein the operation of the DC balance circuit is modified to decouple the pixel voltage from the 6T SRAM memory cell and thereby enable the writing of new data to the 6T cell while relying on circuit capacitance to hold the last voltage state on the pixel mirror for a limited period of time. The ability to load data while holding a previous state is a common requirement for field sequential color display systems wherein the color fields are shown in a time sequence rather than simultaneously, thus enabling all colors to be generated by a single display. Various techniques such as added memory devices within the pixel have been disclosed in competing products, but at some expense in design complexity and subsequent yield.
A weakness of this approach is that because the voltage on the cell cannot be changed during that time the liquid crystal cell cannot be DC balanced during that interval. Various obvious schemes such as alternating the field direction between successive instances are available but not ideal.
Another weakness of this approach is that it does not allow the liquid crystal cell to be reset to a known state during the re-write interval. If there is a need to drive the display to a known dark state to minimize color channel data cross-coupling then that must be done by writing the entire array to a dark state logic setting before the DC balance circuit is invoked to permit rewriting the display memory array to a new data state. This requires that the illumination source be interrupted to permit these operations to take place without degrading the appearance of the display.
application Ser. No. 10/435,427 ('427 application), filed by an inventor of this application, discloses a modulation method compatible with the digital display system disclosed herein. A first row write action takes place on a given row, followed by a second row write action separated from the first row write action by one or more rows, this being following by a third row write action separated from the second row write action by one or more rows, and so forth until a predetermined number of rows have been written with a plurality of different row spacings, whereupon the pattern is repeated after moving the initial row write action by a predetermined spacing, normally one row. The rate of movement of the set of row write actions along the rows of the display and the spacing between the row write actions determines how long the pixels of a row modulates the display according to the data loaded into them. Through practice and experimentation, predetermined spacings may be set up that generate a desired gray scale range. The application also discloses a method of ordering data for higher order bits into thermometer segments in which the higher order bits are always populated in the same order, thereby reducing the data phase errors that cause dynamic false contours and nematic liquid crystal lateral field effects. The use of multiple write actions in this manner is often referred to by the inventor as “multiple write pointers”, “swath modulation” or “MegaMod”.
The modulation method disclosed in the '427 application must be adapted and modified for use in field sequential color displays because of the extended time the method of '427 require to render the entire display into an image data state for a new color.
application Ser. No. 11/740,244 ('244 application), filed by an inventor of this application, discloses a modulation method compatible with the display disclosed herein, in which data displayed on a row is terminated through an instruction embedded in the write data delivered to a different row that writes all storage elements on that row to a single predetermined data value, normally representing a dark state. The selection of a row write action in which to embed to embed the termination instruction is based primarily on the desired elapsed time since the first row write action and secondarily on the availability the embedded instruction slot on the second row write action. The invention was originally conceived as a means for reducing errors in the length of the modulation segments created according to application Ser. No. 10/435,427 ('427 application) previously described. One form of correction disclosed in the '244 application is means for providing a gray scale modulation segment of shorter duration than the shortest bit duration available in the modulation method of the '427 application.
For these reasons, there is still need in the art of LCOS display to provide improved system configurations and to provide alternative means to deliver voltages to pixel mirrors that overcome these limitations.